In digital-to-analog (D/A) conversion circuits, it is desirable to obtain high precision conversion using low precision components. Sigma-delta modulators are often employed in pursuit of this object. In particular, sigma-delta converters allow a high-resolution signal to be translated to a lower resolution signal implementable using standard lower precision components. FIG. 1 illustrates an exemplary prior art sigma-delta conversion circuit denoted generally by the reference numeral 100. The sigma-delta conversion circuit 100 includes a sigma-delta modulator 102 and a digital-to-analog converter (DAC) 106.
The sigma-delta modulator 102 includes integrators 108 and 110, a quantizer 116, an adder 118, and a gain factor 112 in a feedback loop. The output of the quantizer 116 is provided as negative feedback to the summation circuit 118 and to the input of gain block 112. The output of the gain block 112 is provided as negative feedback to another summation circuit 114. The summation circuit 114 receives, as its other input, a digital input signal 120. For example, the digital input 120 may be 17 bit user data provided in a sequential stream. The quantizer 116 may be a 3-bit quantizer, for example. The input of integrator 108 is connected to the output of summation block 114. The output of integrator 108 is connected to an input of adder 118. The output of adder 118 is connected to the input of summation block 110. The output of summation block 110 drives the input of quantizer 116.
A clock source 104 clocks the digital-to-analog converter 106. The clock circuit 104 generally requires a high frequency crystals, such as a 55.2 MHz crystal 122, for clocking the digital-to-analog converter 106. A high frequency crystal is disadvantageous since high frequency crystals are generally very expensive and therefore limit the market acceptance of products in which they are incorporated.
One approach to decreasing the costs of the clocking circuit of FIG. 1 is to employ a lower frequency crystal in the clocking circuit along with a phase locked loop (PLL) frequency multiplier. For example, FIG. 2 illustrates a prior art sigma-delta conversion circuit 200 employing a clocking circuit 204 with a slower and lower-cost 27.6 MHz crystal 222, as opposed to a 55.2 MHz crystal. In order to achieve the same clock speed (55.2 MHz) as in the circuit of FIG. 1 a phase locked loop (PLL) clock doubler 205 is provided at the output of the clock circuit 204. The output of the phase locked loop clock doubler 205 is provided to a clock input of the digital-to-analog converter 206 in FIG. 2. The PLL is needed in FIG. 2 because the sigma-delta conversion circuit signal to noise ratio will degrade significantly if the clock speed is decreased by a factor of 2.
While the circuit of FIG. 2 can be an acceptable solution to the cost issue, the design and manufacturability of the pll 205 in FIG. 2 makes the solution not attractive. FIG. 2 adds complexity via the phase locked loop clock doubler circuit 205. The introduction of the phase locked loop clock doubler circuit 205 is further disadvantageous in that it introduces undesirable clock jitter noise across a wide frequency spectrum of the digital-to-analog converter clock signal. Clock jitter on the digital to analog converter clock signal will mix in the frequency domain with the digital input data to the digital-to-analog converter and produce serious degradation in the noise floor of the converter. For sigma-delta converter circuits, the clock jitter requirements to limit this degradation are extreme, requiring difficult PLL design. Therefore, while FIG. 2 solves the cost issue associated with the conversion circuit, it creates design and manufacturability problems.
For example, FIG. 3 illustrates an exemplary x-y plot of power spectral density (PSD) versus frequency. This graph 300 is representative of the characteristics of the sigma-delta conversion circuit 200 in FIG. 2. The graph 300 shows the power spectrum of the quantization noise 302 and the power spectrum of the phase locked loop induced clock jitter 304. The phase locked loop (PLL) induced clock jitter 304 results from imperfections in the performance of the phase locked loop 205. The quantization noise 302 results from converting the 17 bit input stream down to 3 bits at the output of the 3-bit quantizer 216.
As can be seen in FIG. 3, there is substantial overlap between the quantization noise 302 and phase locked loop induced clock jitter 304. As is known in the art, the digital to analog conversion process can be mathematically modeled such that the there is a "mixing" of the clock jitter with the digital data in the digital to analog converter. This mixing function is equivalent to convolving the spectra of the clock jitter and the digital data to arrive at the spectrum of the output signal of the digital to analog converter. In this process, the jitter spectrum will combine with the quantization noise spectrum in a similar frequency region and raise the noise floor in the signal band near dc. That is, quantization noise 302 and the phase locked loop induced clock jitter 304 will undesirably mix in the digital to analog conversion process, resulting in degraded signal quality at the output of DAC 206, a degradation that has been measured to be as high as 40 dB in some circumstances.
Therefore, the use of a higher frequency crystal suffers from cost limitations, while and the use of lower frequency crystal with a PLL results in the creation of wide-band clock jitter that results in degraded performance in the digital-to-analog conversion process.
Thus, while the use of a lower frequency crystal is desirable from a cost standpoint, its use results in degraded system performance. As such, there is a need in the integrated circuit (IC) and telecommunications industries for an improved digital-to-analog conversion architecture having both high performance and low cost.